AND
MT, SSE2, Family10h
FwStatus | fwiAnd_8u_C1IR | ( | const Fw8u * pSrc, int srcStep, Fw8u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_C3IR | ( | const Fw8u * pSrc, int srcStep, Fw8u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_C4IR | ( | const Fw8u * pSrc, int srcStep, Fw8u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_AC4IR | ( | const Fw8u * pSrc, int srcStep, Fw8u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C1IR | ( | const Fw16u * pSrc, int srcStep, Fw16u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C3IR | ( | const Fw16u * pSrc, int srcStep, Fw16u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C4IR | ( | const Fw16u * pSrc, int srcStep, Fw16u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_AC4IR | ( | const Fw16u * pSrc, int srcStep, Fw16u * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C1IR | ( | const Fw32s * pSrc, int srcStep, Fw32s * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C3IR | ( | const Fw32s * pSrc, int srcStep, Fw32s * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C4IR | ( | const Fw32s * pSrc, int srcStep, Fw32s * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_AC4IR | ( | const Fw32s * pSrc, int srcStep, Fw32s * pSrcDst, int srcDstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_C1R | ( | const Fw8u * pSrc1, int src1Step, const Fw8u * pSrc2, int src2Step, Fw8u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_C3R | ( | const Fw8u * pSrc1, int src1Step, const Fw8u * pSrc2, int src2Step, Fw8u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_C4R | ( | const Fw8u * pSrc1, int src1Step, const Fw8u * pSrc2, int src2Step, Fw8u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_8u_AC4R | ( | const Fw8u * pSrc1, int src1Step, const Fw8u * pSrc2, int src2Step, Fw8u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C1R | ( | const Fw16u * pSrc1, int src1Step, const Fw16u * pSrc2, int src2Step, Fw16u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C3R | ( | const Fw16u * pSrc1, int src1Step, const Fw16u * pSrc2, int src2Step, Fw16u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_C4R | ( | const Fw16u * pSrc1, int src1Step, const Fw16u * pSrc2, int src2Step, Fw16u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_16u_AC4R | ( | const Fw16u * pSrc1, int src1Step, const Fw16u * pSrc2, int src2Step, Fw16u * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C1R | ( | const Fw32s * pSrc1, int src1Step, const Fw32s * pSrc2, int src2Step, Fw32s * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C3R | ( | const Fw32s * pSrc1, int src1Step, const Fw32s * pSrc2, int src2Step, Fw32s * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_C4R | ( | const Fw32s * pSrc1, int src1Step, const Fw32s * pSrc2, int src2Step, Fw32s * pDst, int dstStep, FwiSize roiSize ); | |
FwStatus | fwiAnd_32s_AC4R | ( | const Fw32s * pSrc1, int src1Step, const Fw32s * pSrc2, int src2Step, Fw32s * pDst, int dstStep, FwiSize roiSize ); |
dstStep | Destination buffer step size (width of the buffer in bytes). | |
pDst | Pointer to a location in a destination buffer. | |
pSrc | Pointer to a location in a source buffer. | |
pSrc1 | Pointer to a location in source buffer one. | |
pSrc2 | Pointer to a location in source buffer two. | |
pSrcDst | Pointer to a location in a buffer that contains both the source and destination. | |
roiSize | Specifies the height and width of an ROI. | |
src1Step | Source buffer one step size (width of the buffer in bytes). | |
src2Step | Source buffer two step size (width of the buffer in bytes). | |
srcDstStep | Source and destination buffer step size in bytes (width of both buffers in bytes). | |
srcStep | Source buffer step size (width of the buffer in bytes). |
These functions step through ROIs in two source buffers and perform a bitwise logical AND of the data in buffer 1 and the data in buffer 2.
The results can be written back to the source location or to a destination buffer.